View XAL4030-682ME_4150431.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

high voltage, 1.2 mhz/600 khz, 800 ma, low quiescent current buck regulator data sheet adp2370 /adp2371 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other r i ghts of third parties that may result f rom its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one te chnology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2012 analog devices, inc. all rights reserved. features input voltage range: 3.2 v to 15 v, output current: 800 ma quiescent current < 14 a in power saving mode (psm) > 90% efficiency force pwm pin (sync), 600 khz/1.2 mhz frequency pin (fsel) fixed outputs: 0.8 v, 1.2 v, 1.5 v, 1.8 v, 2.5 v, 3.0 v, 3.3 v, 5 v, and adjustable option 100% duty cycle capability initial accuracy: 1% low shutdown current: <1. 2 a quick output discharge (qod) option synchronizable to an external clock 8- lead , 0.75 mm 3 mm 3 mm lfcsp (qfn) package supported by adisimpowe r design tool applications portable and battery - powered equipment automatic meter readers (wsn) point of sales and transaction processing instruments medical instruments medium format display tablets and pads typical application circuit adp2370/ adp2371 fsel en power good v out = 3.3v v in = 6v c in 10f c out 10f agnd (exposed pad) vin sync on off 1.2mhz 600khz sw pg pgnd fb 1 2 3 4 8 7 6 5 09531-001 figure 1. general description the adp2370 / adp2371 are high efficiency, low quiescent current, 800 ma buck ( step - down ) dc - to - dc converter s in small 8 -lead, 3 mm 3 mm lfcsp (qfn) packages. the total solution requires only three tiny external components. the buck regulator uses a proprietary high speed current mode, constant frequency pwm control scheme for excellent stability and transient response. the nee d for an external rectifier is elimi - nated by using a high efficiency synchronous rectifier architecture . to ensure the longest battery life in portable applications, the adp2370 / adp2371 employ a power saving variable frequency mode that reduces the switching frequency under light load conditions. the adp2370 / adp2371 operate from input voltages of 3.2 v to 15 v allowing the use of multiple alkaline/nimh, lithium cells, or other standard power sources. the adp2370 / adp2371 offer multiple options for setting the operational frequency. the adp2370 / adp2371 can be synchro - nized to a 600 khz to 1.2 mhz external clock or it can be forced to operate at 600 khz or 1.2 mhz via the fsel pin. the adp2370 / adp2371 can be forced to operate in pwm mode (fpwm) when noise considerations are more important than efficiency. a power - good output is available to indicate when the output voltage is below 92% of its nominal value. the adp2371 is identical to the adp2370 except that the adp2371 includes the addition of an integrated switched resistor, quick output discharge function (qod) that auto - matically discharges the output when the device is disabled. both devices include an internal power switch and a syn chronous rectifier for minimal external part count and high efficiency. the adp2370 / adp2371 also include internal soft start and internal compensation for ease of use . during a logic controlled shutdown, the input is disconnected from the output and the regulator draws less than 1.2 a from the input source. other key features include undervoltage lockout to prevent deep battery discharge and soft start to prevent input overcurrent at startup. short - circuit protection and thermal over - load protection circuits prevent damage under adve rse conditions. the adp2370 / adp2371 each use one 0805 capacitor, one 1206 capacitor, and one 4 mm 4 mm inductor. the total solution size is about 53 mm 2 resulting in a very small footprint solution to meet a variety of portable applications.
adp2370/adp2371 data sheet rev. a | page 2 of 32 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? typical application circuit ............................................................. 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? recommended specifications: capacitors ................................ 5 ? absolute maximum ratings ....................................................... 6 ? thermal data ................................................................................ 6 ? thermal resistance ...................................................................... 6 ? esd caution .................................................................................. 6 ? pin configuration and function descriptions ............................. 7 ? typical performance characteristics ............................................. 8 ? buck output .................................................................................. 8 ? theory of operation ...................................................................... 20 ? pwm operation ......................................................................... 20 ? psm operation ........................................................................... 21 ? features descriptions ..................................................................... 22 ? precision enable ......................................................................... 22 ? forced pwm or pwm/psm selection .................................... 22 ? quick output discharge (qod) function ............................. 22 ? short-circuit protection ............................................................ 22 ? undervoltage lockout ............................................................... 22 ? thermal protection .................................................................... 22 ? soft start ...................................................................................... 22 ? current limit .............................................................................. 22 ? 100% duty cycle ........................................................................ 23 ? synchronizing ............................................................................. 23 ? power good ................................................................................ 24 ? applications information .............................................................. 25 ? adisimpower design tool ....................................................... 25 ? external component selection ................................................ 25 ? selecting the inductor ................................................................ 25 ? output capacitor ........................................................................ 25 ? input capacitor ........................................................................... 25 ? adjustable output voltage programming .............................. 25 ? efficiency ..................................................................................... 26 ? recommended buck external components .......................... 26 ? capacitor selection .................................................................... 28 ? thermal considerations ................................................................ 29 ? pcb layout considerations ...................................................... 30 ? packaging and ordering information ......................................... 32 ? outline dimensions ................................................................... 32 ? ordering guide .......................................................................... 32 ? revision history 5/12rev. 0 to rev. a changed voltage range for sw to pgnd and ground plane from ?0.3 v to vin + 0.3 v to ?0.7 v to vin + 0.3 v ............... 6 changes to ordering guide .......................................................... 32 4/12revision 0: initial version
data sheet adp2370/adp2371 rev. a | page 3 of 32 specifications v in = v out + 1 v or 3.2 v, whichever is greater , en = v in , i out = 100 ma, c in = 10 f, c out = 10 f , t a = 25 c for typical specifications, t j = ? 40 c to + 125c for minimum/maximum specifications , unless otherwise noted . table 1 . parameter symbol test conditions /comments min typ max unit supply input vol tage range v in 3.2 15 v quiescent current i q- psm fsel = v in , sync = 0 v, n o l oad, device not switching 1 3.5 a i q- pwm fsel = v in , sync = v in , no load , device not switching 7 25 a i sw - pwm fsel = v in , sync = v in , n o l oad, device switching 5.7 ma shutdown current i shut en = gnd, t j = ? 40 c to +85c 1. 2 3 .5 a fixed output output current i out 800 ma fixed output accuracy v out initial set point, i out = 250 ma, t j = 25c ?1 +1 % i out = 250 ma ? 1.5 + 1.5 % no load to full load, pw m mode ?3 +3 % adjustable output feedback voltage v fb 0.8 v feedback voltage accuracy v fb - tol initial set point, i out = 250 ma, t j = 25c ?1 +1 % output voltage range v out - adj n o load to full load 0.8 14 v fixed and adjustable output load regulation ?v out /?i out no load to full load 0.125 %/a line regulation ?v out /?v in i out = 250 ma 0.0 1 %/v efficiency eff i out = 250 ma, v in = 7.2 v, v out = 3.3 v 92 % overcurrent frequency foldback threshold rising oc foldback - rise % of v out , v out rising 50 % falling oc foldback - fal l % of v out , v out falling 37.5 % psm threshold psm threshold v in = 7.2 v, v out = 3.3 v 170 ma feedback pin input current fixed i fb -f ixed fixed output voltage model 2.5 a adjustable i fb -adjust adjustable output voltage model 10 na minimum on time on - time min v in < 5.5 v 65 100 ns v in > 5.5 v 40 60 ns soft start time ss time when en rises from 0 v to v in , and v out = 0.9 v out 350 s active pull - down resistance ( adp2371 ) r pull - down 260 400 power switch p- channel on resistance rds on -p v in > 5.5 v, i out = 400 ma 400 m v in < 5.5 v, i out = 400 ma 500 m n- channel on resistance rds on -n v in > 5.5 v, i out = 400 ma 28 0 m v in < 5.5 v, i out = 400 ma 40 0 m current limit p - channel i lim-p peak inductor current 1200 1300 ma n- channel i lim-n peak inductor current 500 550 ma leakage current i leak - sw p- channel 0.01 1 a n- channel 0.01 1 a oscilla tor oscillator frequency f osc fsel = v in , 3.2 v v in 15 v 1.0 1.2 1.4 mhz fsel = 0 v, 3.2 v v in 15 v 500 600 700 khz
adp2370/adp2371 data sheet rev. a | page 4 of 32 parameter symbol test conditions /comments min typ max unit frequency synchronization range f sync_range fsel = 0 v, 3.2 v v in 15 v 400 800 khz fsel = v in , 3.2 v v in 15 v 0.8 1.6 mhz synchronization threshold high sync high 3.2 v v in 15 v 1.2 v low sync low 3.2 v v in 15 v 0.4 v hysteresis sync hys 3.2 v v in 15 v 200 mv typical sync duty cycle range sync duty v in (1.2 mhz), 3.2 v v in 5 v , fsel = v in 20 55 % v in (1.2 mhz), 5 v v in 15 v , fsel = v in 20 70 % sync pin leakage current sync lkg sync = 0 v or sync = v in 0.05 1 a fsel threshold 3.2 v v in 15 v high fesl high 1 v low fsel low 0.4 v hysteresis fsel hys 125 mv fsel pin leakage current fsel lkg fsel = 0 v or fsel = v in 0.04 1 a power good (pg pin) pg threshold 3 .2 v v in 15 v rising pg rise 92 95 % falling pg fal l 82.5 87 % hysteresis pg hys 5 % pg output low pg low pull - up current < 1 ma 0.3 v pg delay r ising pg delayrise v out crossing pg rising threshold, p ull - up current < 1 ma 20 s f alling pg delayfall v out crossing pg falling threshold, p ull - up current < 1 ma 0.5 s pg leakage pg lkg 0.04 1 a undervoltage lockout (uvlo) input voltage rising uvlo rise 3.19 v input voltage falling uvlo fal l 2.80 v hysteresis uvlo hys 190 mv en able input standby (en pin) 3.2 v v in 15 v en input logic v high en stby -high 1 low en stby - low 0.4 v hysteresis en stby - hys 125 mv en able input precision (en pin) 3.2 v v in 15 v en input logic high en high 1.135 1.2 1.26 v low en low 1.045 1.1 1.155 v hysteresis en hys 100 mv en input leakage current i en - lkg en = v in or gnd 0.05 1 a en input delay time ti en - dly for v out = 0 v to 0.1 v out when en rises from 0 v to v in 70 s thermal shutdown 3.2 v v in 15 v thermal shutdown threshold ts sd t j rising 150 c thermal shutdown hysteresis ts sd - hys 15 c
data sheet adp2370/adp2371 rev. a | page 5 of 32 recommend ed specifications: capacitors table 2 . parameter symbol test conditions /comments min typ max unit minimum input and output capacitance 1 c min t a = ?40 c to +125c 6.5 10 f capacitor esr r esr t a = ?40c to +125c 1 10 m 1 the minimum input and output capacitance should be greater than 7 f over the full range of operating conditions. the full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. x7r - and x5r - type capacitors are recommended; y5v and z5u capacitors are not recommended for use with any buck.
adp2370/adp2371 data sheet rev. a | page 6 of 32 ab solute maximum ratin gs table 3. parameter rating vin to pgnd and ground plane ?0.3 v to + 17 v sw to pgnd and ground plane ?0. 7 v to vin + 0.3 v fb to pgnd and ground plane ?0. 3 v to +6 v en to pgnd and ground plane ?0.3 v to +1 7 v pg to pgnd and ground plane ?0.3 v to +17 v sync to pgnd and ground plane ?0. 3 v to +17 v fsel to pgnd and ground plane ?0.3 v to +17 v temperature range storage ?65c to +150c operating ambient ?40c to +85c operating junction ?40c to +1 25c soldering conditions jedec j - std -020 stress es a bo ve thos e l isted under absolute maxim um ratin gs ma y c ause permanent damag e to the device. this is a stress rating only; fu nctional operation of the d ev ice at these or any other co nditio ns abo ve those indicated in the operatio na l section of th is speci fi cat ion is not implied. expo su re to absolu te ma ximum rat in g conditions fo r e xtended periods may a ff ect de vi ce reliability. thermal data absolute maximum ratings apply individually only, not in com - bination. exceeding the junction temperature ( t j ) limit can cause damage to t he adp2370 / adp2371 . monitoring ambient temperature does not guarantee that t j is within the specified temperature limits. t he maximum ambient temperature may require derating i n applications with high power dissipat ion and po or thermal resistance . in applications with moderate power dissipation and low printed circuit board ( pcb ) thermal resistance, the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits . the junction temperature of the device is depen dent on the ambient temperature, the power dissipation of the device , a nd the junction to ambient thermal resistance of the package ( ja ). maximum junction temperature (t j ) is calculated from the ambient temperature (t a ) and power dissipation (p d ) using the formula t j = t a + ( p d ja ) junction - to - ambient thermal resistance ( ja ) of the package is ba sed on modeling and calculation using a 4- layer board. ja is highly dependent on the application and board layout. in applica - tions where high maximum power dissipation exists, close attention to thermal board design is required. the value of ja can vary , depending on pcb material, layout, and environmental con - ditions. the specified values of ja are based on a 4- layer, 4 in. 3 in. circuit board . see jesd 51 -7, high effective thermal conduc - tivity test board for leaded surface mount packages , for deta iled information on board constr uction. for more information, see application note an - 772 , a design and manufacturing guide for the lead frame chip scale package (lfcs p) . jb is the junction to board thermal characterization parameter with units of c/w. the jb of the package is based on modeling and calculation using a 4- layer board. the jesd51 - 12, guidelines for reporting and using electronic package thermal information , states that thermal characterization parameters are not the same as thermal resistances . jb measures the component power flowing through multiple thermal paths rather than a single path as in thermal resistance, jb . therefore, jb thermal paths include convection from the top of the package as well as radiation from the package, factors that make jb more useful in real - world applications. maximum junction temperature (t j ) is calculated from the board temperature (t b ) and power dissipation (p d ) using the formula t j = t b + ( p d jb ) for more detail ed information regarding jb , see jesd51 - 12 and jesd51 -8, integrated circuit thermal test method envi - ronmental conditions junction - to - board . thermal resistance ja and jb are specified for the worst - case cond itions, that is, a device soldered in a circuit board for surface - mount packages. jc is a par ameter for surface - mount packages with top mounted heat sinks . table 4 . thermal resistance package type ja jc jb unit 8- lead 3 mm 3 m m lfcsp 36.7 23.5 17 .2 c/w esd caution
data sheet adp2370/adp2371 rev. a | page 7 of 32 pin configuration and function descripti ons 09531-002 adp2370/adp2371 top view (not to scale) 3en 4sync 1vin notes 1. the exposed pad on the bottom of the package enhances the thermal performance and is electrically connected to ground inside the package. the exposed pad must be connected to the ground plane on the circuit board for proper operation. 2fsel 6 pg 5 fb 8 pgnd 7 sw figure 2. pin configuration table 5 . pin function descriptions pin no. mnemonic description 1 vin power inp ut . 2 fsel frequency select. high = 1.2 mhz, low = 600 khz. 3 en enable. enable input with precision thresholds. 4 sync synchronize. this pin is used to synchronize the device to an external 600 khz to 1.2 mhz clock or forces pwm mode when it is held hi gh. sync held low forces automatic pwm/psm operation. 5 fb feedback . this pin provides feedback from the output . 6 pg power good. pg is an open - drain output. 7 sw switch. this pin serves as the c onnection from the power mosfets to the inductor . 8 pgnd power ground . epad exposed pad . the exposed pad on the bottom of the package enhances the thermal performance and is electrically connected to ground inside the package. the exposed pad must be connected to the ground plane on the circuit board for prope r operation.
adp2370/adp2371 data sheet rev. a | page 8 of 32 typical performance characteristics buck output using recommended inductor value s, i out = 10 ma, c in = c out = 10 f, automatic psm/pwm mode, t a = 25c, unless otherwise noted. 0 5 10 15 20 25 3 4 5 6 7 8 9 10 11 12 13 14 15 16 quiescent current (a) input vo lt age (v) ?40 c ?5 c +25 c +85 c +125 c 09531-003 figure 3 . quiescent supply current vs. input voltage, nonswitching, different temperatures 500 600 550 650 700 750 800 3 4 5 6 7 8 9 10 11 12 13 14 15 fpwm quiescent current (a) input vo lt age (v) ?40 c ?5 c +25 c +85 c +125 c 09531-004 figure 4. fpwm quiescent supply current vs. input voltage, nonswitching, different temperatures 0.55 0.57 0.59 0.61 0.63 0.65 1.10 1.12 1.14 1.16 1.18 1.20 1.22 1.24 1.26 1.28 1.30 ?45 ?25 ?5 15 35 55 75 95 1 15 135 tempera ture (c) 1.2mhz 600 khz frequenc y (mhz) frequenc y (mhz) 09531-005 figure 5 . switching frequency vs . temperatur e, fpwm m ode, v in = 8 v 0.55 0.57 0.59 0.61 0.63 0.65 1.10 1.12 1.14 1.16 1.18 1.20 1.22 1.24 1.26 1.28 1.30 3 5 7 9 11 13 15 tempera ture (c) 1.2mhz 600 khz 09531-006 frequenc y (mhz) frequenc y (mhz) figure 6 . switching frequency vs. input voltage, fpwm m ode 3.10 3.15 3.20 3.25 3.30 3.35 3.40 ?40 ?5 25 85 125 output vo lt age (v) tempera ture (c) 0.1ma 1ma 5ma 10 ma 50 ma 100 ma 300 ma 800 ma 09531-007 figure 7 . output voltage vs. temperature, v out = 3.3 v, v in = 7.3 v, different loads ?40 ?5 25 85 125 output vo lt age (v) tempera ture (c) 09531-008 4.80 4.85 4.90 4.95 5.00 5.05 5.10 5.15 5.20 0.1ma 1ma 5ma 10 ma 50 ma 100 ma 300 ma 800 ma figure 8 . output voltage vs. temperature, v out = 5 v, v in = 7.2 v, different loads
data sheet adp2370/adp2371 rev. a | page 9 of 32 1.15 1.17 1.19 1.21 1.23 1.25 ?40 ?5 25 85 125 output vo lt age (v) tempera ture (c) 0.1ma 1ma 5ma 10 ma 50 ma 100 ma 300 ma 800 ma 09531-009 figure 9 . output voltage vs. temperature, v out = 1.2 v, v in = 4 v, different loads 1.70 1.75 1.80 1.85 1.90 ?40 ?5 25 85 125 output vo lt age (v) tempera ture (c) 0.1ma 1m a 5ma 10 ma 50 ma 100 ma 300 ma 800 ma 09531-010 figure 10 . output voltage vs. temperature, v out = 1.8 v, v in = 7.2 v, different loads 3.10 3.15 3.20 3.25 3.30 3.35 3.40 3 5 7 9 11 13 15 output vo lt age (v) input vo lt age (v) 0.1ma 1ma 5ma 10 ma 50 ma 100 ma 300 ma 800 ma 09531-0 11 figure 11 . line regulation, v out = 3.3 v, different loads 3.10 3.15 3.20 3.25 3.30 3.35 3.40 0.1 1 10 100 1000 output vo lt age (v) load (ma) 3.8v 4. 55 v 6. 05 v 7. 30 v 10 . 55 v 12 . 05 v 15 . 05 v 09531-012 figure 12 . load regulation, v out = 3.3 v 3.10 3.15 3.20 3.25 3.30 3.35 3.40 3 5 7 9 11 13 15 output vo lt age (v) input vo lt age (v) 0.1ma 1ma 5ma 10 ma 50 ma 100 ma 300 ma 800 ma 09531-013 figure 13 . l ine regulation, v out = 5.0 v, different loads 4.80 4.85 4.90 4.95 5.00 5.05 5.10 5.15 5.20 0.1 1 10 100 1000 output vo lt age (v) load (ma) 5.40v 6.00v 7.20v 9.00v 10.80v 12 .0 0v 15 . 05 v 09531-014 figure 14 . load regulation, v out = 5.0 v
adp2370/adp2371 data sheet rev. a | page 10 of 32 1.15 1.16 1.17 1.18 1.19 1.20 1.21 1.22 1.23 1.24 1.25 3 5 7 9 11 13 15 output vo lt age (v) input vo lt age (v) 0.1ma 1ma 5ma 10 ma 50 ma 100 ma 300 ma 800 ma 09531-015 figure 15 . line regulation, v out = 1.2 v, different loads 1.15 1.16 1.17 1.18 1.19 1.20 1.21 1.22 1.23 1.24 1.25 0.1 1 10 100 1000 output vo lt age (v) load (ma) 3.20v 3.95v 5.45v 7.20v 9.95v 1 1.95v 15 .20v 09531-016 figure 16 . load regulat ion, v out = 1.2 v 1.70 1.75 1.80 1.85 1.90 3 5 7 9 11 13 15 output vo lt age (v) input vo lt age (v) 0.1ma 1ma 5ma 10 ma 50 ma 100 ma 300 ma 800 ma 09531-017 figure 17 . line regulation, v out = 1.8 v, different loads 1.70 1.75 1.80 1.85 1.90 0.1 1 10 100 1000 output vo lt age (v) load (ma) 09531-018 3.20v 3.95v 5.45v 7.20v 9.95v 1 1.95v 15 .20v figure 18 . load regulation, v out = 1.8 v 0 10 20 30 40 50 60 70 80 90 100 0.01 0.10 1.0 10 100 1000 efficienc y (%) load (ma) 09531-019 3. 80 v 4. 55 v 6. 05 v 7. 30 v 10 . 55 v 12 . 05 v 15 . 05 v figure 19 . efficiency vs. load current, v out = 3.3 v, different input voltages 0 10 20 30 40 50 60 70 80 90 100 0.01 0.10 1.0 10 100 1000 efficienc y (%) load (ma) 09531-020 ?40 c ?5 c +25 c +85 c +125 c figure 20 . efficiency vs. load current, v out = 3.3 v, different temperatures, v in = 7.3 v
data sheet adp2370/adp2371 rev. a | page 11 of 32 0 10 20 30 40 50 60 70 80 90 100 0.01 0.10 1.0 10 100 1000 efficienc y (%) load (ma) 09531-021 5.4v 6.0v 7.2v 9.0v 10 . 8v 1 2.8v 15 .0v figure 21 . efficiency vs. load current, v out = 5.0 v, different input voltages 0 10 20 30 40 50 60 70 80 90 100 0.01 0.10 1.0 10 100 1000 efficienc y (%) load (ma) 09531-022 ?40 c ?5 c +25 c +85 c +125 c figure 22 . efficiency vs . load current, v out = 5.0 v, different temperatures 0 10 20 30 40 50 60 70 80 90 100 0.01 0.10 1.0 10 100 1000 efficienc y (%) load (ma) 09531-023 3.20v 3.95v 5. 5 0v 7.20v 9.9 5v 12 .45v 15 . 20v figure 23 . efficiency vs. load current, v out = 1.2 v, different input voltages 0 10 20 30 40 50 60 70 80 90 100 0.01 0.10 1.0 10 100 1000 efficienc y (%) load (ma) 09531-024 ?40 c ?5 c +25 c +85 c +125 c figure 24 . e fficiency vs. load current, v out = 1.2 v, different temperatures, v in = 4 v 0 10 20 30 40 50 60 70 80 90 100 0.01 0.10 1.0 10 100 1000 efficienc y (%) load (ma) 09531-025 3.20v 3.95v 5. 5 0v 7.20v 9.9 5v 12 .45v 15 . 20v figure 25 . efficiency vs. load current, v out = 1.8 v, different input voltages 0 10 20 30 40 50 60 70 80 90 100 0.01 0.10 1.0 10 100 1000 efficienc y (%) load (ma) 09531-026 ?40 c ?5 c +25 c +85 c +125 c figure 26 . efficiency vs. load current, v ou t = 1.8 v, different temperatures, v in = 4 v
adp2370/adp2371 data sheet rev. a | page 12 of 32 40 45 50 55 60 65 70 75 80 85 90 0.01 0.1 1 10 100 1000 efficiency (%) load (ma) 600khz 1.2mhz 09531-027 figure 27 . efficiency vs . load current, different switching frequency, v out = 1.8 v, v in = 9 v ch1 500ma ? b w ch3 1.00v b w ch2 20.0mv b w m10.0s a ch3 4.56v 1 2 3 t 11.00% v out v in 09531-028 inductor current figure 28 . line transient, v out = 1.8 v, psm m ode, 100 ma , v in1 = 4 v to 5 v, 2 s rise time, c in = 3.3 f m10.0s a ch3 4.64v 1 t 11.20% v out v in inductor current 09531-029 ch1 200ma ? b w ch3 1.00v b w ch2 20.0mv b w figure 29 . line transient, v out = 1.8 v, pwm mode, 800 ma, v in1 = 4 v to 5 v, 2 s rise time, c in = 3.3 f m10.0s a ch3 4.56v 2 1 3 t 11.0% v out v in inductor current 09531-030 ch1 500ma ? b w ch3 1.00v b w ch2 20.0mv b w figure 30 . line transient, v out = 1.2 v, psm mode, 100 ma, v i n1 = 4 v to 5 v, 2 s rise time, c in = 3.3 f m10.0s a ch3 5.44v 1 2 3 t 10.80% v out v in inductor current 09531-031 ch1 500ma ? b w ch3 1.00v b w ch2 10.0mv b w figure 31 . line transient, v out = 1.2 v, pwm mode, 800 ma, v in1 = 4 v to 5 v, 2 s rise time, c in = 3.3 f m10.0s a ch3 6.78v 1 2 3 t 11.40% v out v in inductor current 09531-032 ch1 200ma ? b w ch3 1.00v b w ch2 20.0mv b w figure 32 . line transient, v out = 3.3 v, psm mode, 100 ma, v in1 = 6 v to 7 v, 2 s rise time, c in = 3.3 f
data sheet adp2370/adp2371 rev. a | page 13 of 32 m10.0s a ch3 6.78v 1 2 t 11.40% v out v in inductor current 09531-033 ch1 200ma ? b w ch3 1.00v b w ch2 10.0mv b w figure 33 . line transient, v out = 3.3 v, pwm mode, 800 ma, v in1 = 6 v to 7 v, 2 s rise time, c in = 3.3 f m10.0s a ch3 6.74v 1 2 3 t 10.60% v out v in inductor current 09531-034 ch1 200ma ? b w ch3 1.00v b w ch2 50.0mv b w figure 34 . line transient, v out = 5 v, psm mode, 100 ma, v in1 = 6 v to 7 v, 2 s rise time, c in = 3.3 f m10.0s a ch3 6.52v 1 2 t 11.00% v out v in inductor current 09531-035 ch1 200ma ? b w ch3 1.00v b w ch2 10.0mv b w figure 35 . line transient, v out = 5 v, pwm mode, 800 ma, v in1 = 6 v to 7 v, 2 s rise time, c in = 3.3 f m20.0s a ch1 560ma 1 2 3 t 10.40% 09531-036 ch1 500ma ? b w ch3 500ma ? b w ch2 50.0mv b w load current v out inductor current figure 36 . load transient, v out = 1.8 v, 300 ma to 800 ma, load current rise time = 200 ns m40.0s a ch1 320ma 1 2 3 t 72.00% 09531-037 ch1 500ma ? b w ch3 500ma ? b w ch2 100mv b w load current v out inductor current figure 37 . load transient, v out = 1.8 v, 10 ma to 800 ma, load current rise time = 200 ns m10.0s a ch1 76.0ma 1 2 3 t 50.40% 09531-038 ch1 100ma ? b w ch3 200ma ? b w ch2 20.0mv b w load current v out inductor current figure 38 . load transient, v o ut = 1.8 v,10 ma to 110 ma, load current rise time = 200 ns
adp2370/adp2371 data sheet rev. a | page 14 of 32 m20.0s a ch1 208ma 1 2 3 t 50.40% 09531-039 ch1 200ma ? b w ch3 200ma ? b w ch2 50.0mv b w load current v out inductor current figure 39 . load transient, v out = 1.8 v,100 ma to 300 ma, load current rise time = 200 ns m40.0s a ch1 580ma 1 2 3 t 10.20% 09531-040 ch1 500ma ? b w ch3 500ma ? b w ch2 50.0mv b w load current v out inductor current figure 40 . load transient, v out = 3.3 v, 300 ma to 800 ma, load current rise time = 200 ns m40.0s a ch1 530ma 1 2 3 t 71.80% 09531-041 ch1 500ma ? b w ch3 500ma ? b w ch2 200mv b w load current v out inductor current figure 41 . load transient, v out = 3.3 v, 10 ma to 800 ma, load current rise time = 200 ns m20.0s a ch1 46.0ma 1 2 3 t 50.40% 09531-042 ch1 100ma ? b w ch3 200ma ? b w ch2 50.0mv b w load current v out inductor current figure 42 . load transient, v out = 3.3 v, 10 ma to 110 ma, lo ad current rise time = 200 ns m20.0s a ch1 184ma 1 2 3 t 29.80% 09531-043 ch1 200ma ? b w ch3 200ma ? b w ch2 50.0mv b w load current v out inductor current figure 43 . load transient, v out = 3.3 v, 100 ma to 300 ma, load current rise time = 200 ns m10.0s a ch1 560ma 1 2 3 t 10.40% 09531-044 ch1 500ma ? b w ch3 500ma ? b w ch2 50.0mv b w load current v out inductor current figure 44 . load transient, v out = 1.2 v, 300 ma to 800 ma, load current ris e time = 200 ns, v in = 5 v
data sheet adp2370/adp2371 rev. a | page 15 of 32 m40.0s a ch1 320ma t 72.00% 09531-045 ch1 500ma ? b w ch3 500ma ? b w ch2 100mv b w load current v out inductor current 1 2 3 figure 45 . load transient, v out = 1.2 v, 10 ma to 800 ma, load current rise time = 200 ns, v in = 5 v m10.0s a ch1 112ma t 50.40% 09531-046 ch1 100ma ? b w ch3 500ma ? b w ch2 20.0mv b w load current v out inductor current 1 2 3 figure 46 . load transient, v out = 1.2 v,10 ma to 110 ma, load current rise time = 200 ns, v in = 5 v m20.0s a ch1 220ma 1 2 3 t 50.40% 09531-047 ch1 100ma ? b w ch3 200ma ? b w ch2 50.0mv b w load current v out inductor current figure 47 . load transient, v out = 1.2 v,100 ma to 300 ma, load current rise time = 200 ns, v in = 5 v m20.0s a ch1 530ma 1 2 3 t 10.00% 09531-048 ch1 500ma ? b w ch3 500ma ? b w ch2 100mv b w load current v out inductor current figure 48 . load transient, v out = 5 v, 300 ma to 800 ma, load curre nt rise time = 200 ns, v in = 8 v m40.0s a ch1 320ma 1 2 3 t 72.00% 09531-049 ch1 500ma ? b w ch3 500ma ? b w ch2 200mv b w load current v out inductor current figure 49 . load transient, v out = 5 v, 1 ma to 800 ma, load current rise time = 200 ns, v in = 8 v m20.0s a ch1 80.0ma t 50.40% 09531-050 ch1 100ma ? b w ch3 200ma ? b w ch2 50.0mv b w load current v out inductor current 1 2 3 figure 50 . load transient, v out = 5 v,10 ma to 110 ma, load current rise time = 200 ns, v in = 8 v
adp2370/adp2371 data sheet rev. a | page 16 of 32 m20.0s a ch1 208ma 1 2 3 t 30.40% 09531-051 ch1 200ma ? b w ch3 200ma ? b w ch2 100mv b w load current v out inductor current figure 51 . load transient, v out = 5 v, 100 ma to 300 ma, load current rise time = 200 ns, v in = 8 v m100s a ch1 2.50v 1 2 3 t 10.00% 09531-052 ch1 5.00v b w ch3 200ma ? b w ch2 1.00v b w v in v out inductor current figure 52 . startup, v out = 1.8 v, 10 ma m100s a ch1 2.50v 1 2 3 t 10.00% 09531-053 ch1 5.00v b w ch3 500ma ? b w ch2 1.00v b w v in v out inductor current figure 53 . startup, v out = 1.8 v, 800 ma m100s a ch1 2.50v t 10.00% 09531-054 ch1 5.00v b w ch3 200ma ? b w ch2 2.00v b w v in v out inductor current 1 2 3 figure 54 . startup, v out = 3.3 v, 10 ma m100s a ch1 2.50v t 10.00% 09531-055 ch1 5.00v b w ch2 2.00v b w v in v out inductor current 1 2 3 ch3 500ma ? b w figure 55 . startup, v out = 3.3 v, 800 ma m100s a ch1 2.50v t 10.00% 09531-056 ch1 5.00v b w ch3 200ma ? b w ch2 1.00v b w v in v out 1 2 3 inductor current figure 56 . startup, v out = 1.2 v, 10 ma, v in = 5 v
data sheet adp2370/adp2371 rev. a | page 17 of 32 m100s a ch1 2.50v t 10.00% 09531-057 ch1 5.00v b w ch3 500ma ? b w ch2 500mv b w v in v out inductor current 1 2 3 figure 57 . startup, v out = 1.2 v, 800 ma, v in = 5 v m100s a ch1 2.50v t 10.00% 09531-058 ch1 5.00v b w ch3 200ma ? b w ch2 2.00mv b w v in v out inductor current 1 2 3 figure 58 . startup, v out = 5 v, 10 ma, v in = 7 v m100s a ch1 2.50v t 10.00% 09531-059 ch1 5.00v b w ch3 500ma ? b w ch2 2.00mv b w v in v out inductor current 1 2 3 figure 59 . startup, v out = 5 v, 800 ma, v in = 7 v 0 50 100 150 200 250 3 5 7 9 11 13 15 psm t o pwm threshold (ma) input vo lt age (v) ?40 c ?5 c +25 c +85 c +125 c 09531-060 figur e 60 . psm to pwm mode transition vs. input voltage, different temperatures 800 850 900 950 1000 1050 1 100 1 150 1200 ?60 ?40 ?20 0 20 40 60 80 100 120 140 oc threshold (ma) tempera ture (c) 5.4v 7.2v 12 .0v 15 .0v 09531-061 figure 61 . overcurrent lim it vs. temperature, v out = 5 v, different input voltages 0 0.02 0.04 0.05 0.01 0.03 0 100 200 300 400 500 600 700 800 ripple vo lt age (mv p-p) load current (ma) 3.2v 5 .0v 9 .0v 15v 09531-062 figure 62 . ou tput ripple vs . load current, v out = 1.2 v, different input voltages, auto matic mode
adp2370/adp2371 data sheet rev. a | page 18 of 32 0 0.02 0.04 0.05 0.01 0.03 0 100 200 300 400 500 600 700 800 ripple vo lt age (mv p-p) load current (ma) 3.2v 5 .0v 9 .0v 15v 09531-063 figure 63 . output ripple vs . load current, v out = 1.8 v, different input voltages, auto matic mode 0 0.04 0.06 0.08 0.02 0 100 200 300 400 500 600 700 800 ripple vo lt age (mv p-p) load current (ma) 4.5v 5 .0v 9 .0v 15v 09531-064 figure 64 . outp ut ripple vs . load current, v out = 3.3 v , different input voltages, auto matic mode 0 0.04 0.06 0.08 0.10 0.02 0 100 200 300 400 500 600 700 800 ripple vo lt age (mv p-p) load current (ma) 5.8v 6.0v 9 .0v 15v 09531-065 figure 65 . output ripple vs . load current, v out = 5 v , different input voltages, auto matic mode 0 0.005 0.010 0.015 0.020 0.025 0 100 200 300 400 500 600 700 800 ripple vo lt age (mv p-p) load current (ma) 4v 5v 9v 15v 09531-066 figure 66 . output r ipple vs . load current, v out = 3.3 v , different input voltages, force pwm mode 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 ?40 ?20 0 20 40 60 80 100 120 rds on (?) tempera ture (c) 3 .0v 3.5v 4 .0v 5 .0v 6 .0v 7 .0v 10 .0v 09531-067 figure 67 . pmos rds on vs . temperature at 400 ma, different input voltages 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 ?40 ?20 0 20 40 60 80 100 120 rds on (?) tempera ture (c) 3 .0v 3.5v 4 .0v 5 .0v 6 .0v 7 .0v 10 .0v 09531-068 figure 68 . nmos rds on vs . temperature at 400 ma, different input voltages
data sheet adp2370/adp2371 rev. a | page 19 of 32 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 3 4 5 6 7 8 9 10 rds on (?) input vo lt age (v) 09531-069 ?40 c ?5 c +25 c +85 c +125 c figure 69 . pmos rds on vs . input voltage at 400 ma, different temperatures 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 3 4 5 6 7 8 9 10 rds on (?) input vo lt age (v) 09531-070 ?40 c ?5 c +25 c +85 c +125 c figure 70 . nmos rds on vs . input voltage at 400 ma, different temperatures
adp2370/adp2371 data sheet rev. a | page 20 of 32 theory of o peration slope com p oscill at or de f au l t = 1.2mhz vout 2 frequenc y foldback contro l logic adp2371 on ly soft st art 1.2v en vin sw pgnd fb sync fsel pg 1.0v st andb y en_prec vin 200m a kr uvlo vin pwm psm 0.808v 0.8v vin 1.2 a vin 5v reg vin 2.95v 0.736v 0.8v 0.696v 150c 135c h = fpwm l = pwm/psm h = 1.2mhz l = 600khz thsd fb i slope rds on kr rds on kr p_i limit n_i limit ?0.5 a ? (pwm) 0a ? (psm) i min v sw g m v com p i com p v tol 09531-071 figure 71 . functional block diagram the adp2370 / adp2371 us e a high speed , current mode, con - stant frequency pwm control scheme fo r excellent stab ility and tran sient response. to ensure the longest battery life in portable applications, the adp2370 / adp2371 has a power s aving mode. under light l oad conditions, the output capacitor is charged as needed to maintain regulation ; otherwise , the adp2370 / adp2371 enter sleep mode, a low 14 a quiescent state . the architecture e nsures smooth transitions from pwm mode to and from psm , and maintains high efficiencies at light loads. the following sec - tions describe the two modes of operation and provide detailed descriptions of the adp2370 / adp2371 features. pwm operation the adp2370 / adp2371 pwm mode is a fixed frequen cy, 1.2 mhz typical, current mode architecture. use t he sync pin to synchro nize the reg ulator to an external clock frequency or use the fsel pin to select an internal clock frequency of 600 khz or 1.2 mhz. the adp2370 / adp2371 use a constant slope compensation scheme where the induct or scales with the output voltage. the equation for choosing the inductor for a particular output voltage is sw out f v l = 478.0 2.1 see the applications information section for details regarding choosing an appropriate inductor value. cycle to cycle operation of the pwm mode begins with the falling edge of the internal clock. n ote that when using an external clock , the rising edge synchronize s the regulator and the falling edge is determined by the internal clock, typically a 25 ns pulse width. the falling edge of the clock starts the cycle by turning on the high - side switch, which produces a positive di/dt current in the inductor. the pwm comparator controls when the high - side switch turns off. the positive input of the comparator monitors the peak inductor current via the sw node.
data sheet adp2370/adp2371 rev. a | page 21 of 32 the negative side of the comparator input voltage is set by the voltage control loop minus the slope compensation. when the high - side switch turns off , the low - side switch turns on for the remain der of the clock period. while in pwm/psm mode , the low - side switch turn s off when the inductor current reaches zero, operating in discontinuou s conduction (dcc) mode. if sync is tied high to force the device into p wm only mode , the low - side switch stay s on until the next clock cycle or until the inductor current rea ches the negative current limit . psm operation the adp2370 / adp2371 smooth ly transition to the variable frequency psm operation. the adp2370 / adp2371 select a minimum current value, i min , for the peak current of the inductor based on the input and output voltages. the design of the i min value is based on the recommended inductor values. deviating from the recommended inductor value for a particular output voltag e result s in shifting the psm to pwm threshold and could result in the device entering dcc mode. as long as the required peak inductor current is above i min , the regulator remain s in pwm mode. as the load decreases, the psm circ uitry prevents the peak ind uctor current from dropp ing below the psm peak current value. this circuitry causes the regulator to supply more current to the output filter than the load requires , resulting in the output voltage increasing and the output of the internal compensation no d e of the error amplifier, v comp , decreasing . when the fb pin voltage rises above 1% of the nominal output voltage and the v comp node voltage is below a predetermined psm threshold voltage level , the regulator enters sleep mode . while in sleep mode, the hi gh - side and low -s ide switches and a majority of the circuitry are disabled to allow for a low sleep mode quiescent current as well as high efficiency performance. d uring sleep mode , the output voltage decreases as the output capacitor discharges into the load. fixed frequency operation starts w hen the fb voltage reaches the nominal out put voltage. when the load requirement increases past the i min peak current level , the v comp node rise s and the pwm control loop sets the duty cycle. while the part is enteri ng and exiting sleep mode, t he psm voltage ripple is larger than 1% because of the delay in the comparators. figure 72 and figure 73 illustrate how the output volt age and inductor current change with load s and transitions in and out of psm operation. the output voltage ripple in psm is ~40 mv p- p, and the ripple in pwm is <10 mv p- p. m20.00s a ch1 156ma t 50.40% 09531-072 ch1 200ma ? b w ch3 200ma ? b w ch2 50.0mv b w load current v out inductor current 1 2 3 figure 72 . psm to pwm transition waveforms, v out = 1.8 v, 10 ma l oad to 300 ma load m20.00s a ch1 156ma t 50.40% 09531-073 ch1 200ma ? b w ch3 200ma ? b w ch2 50.0mv b w v out inductor current 1 2 3 load current figure 73 . pwm to psm transition waveforms, v out = 1.8 v, 300 ma l oad to 10 ma load
adp2370/adp2371 data sheet rev. a | page 22 of 32 features description s precision enable the e nable circuit of the adp2370 / adp2371 minimizes the input current during shutdown and simultaneously provid es an accurate e nable threshold. when the e nable input voltage is below 400 mv, the regulators are in shutdown mode and the supply current is typically 1.2 a. as the e nab le input voltage rises above the standby enable threshold of 1.0 v, the internal bia s currents and voltages are activated, turning on the precision enable circuitry. this allows the precision enable circuitry to detect accurately when the en pin voltage ex ceeds the precision enable rising threshold of 1.2 v. forced pwm or pwm/ps m selection connecting the sync pin to a voltage greater than 1.2 v forces the devic e to operate permanently in the pwm mode. this means that the adp2370 / adp2371 co ntinue to operate at a fixed fre - quency even when the output current is less than the pwm/psm threshold. in pwm mode, the efficiency is lower compared to the psm mode during light lo ads. the low - side nmos remains on when the output current drops to less than zero thereby preventing the device from entering discontinuous conduction (dcc) mode. it is possible to switch from fpwm mode to the power - save mode during operation by pulling th e sync pin low. the flexible configuration of the sync pin during operation of the device allows for efficient power management. connecting the sync pin to a voltage less than 0.4 v allows the part to operate in either pwm or psm modes, depending on the ou t put current. whenever the average output current goes below the pwm/psm threshold, the adp2370 / adp2371 enter psm mode operation. during psm mode the part operates with reduced switching frequency and with a minimal quiescent cur - rent t o maintain high efficiency. the low - side nmos turn s off when the output current reaches zero , causing the part to operate in dcc mode . quick output dischar ge (qod) function the adp2371 includes an output discharge resistor t hat force s the output voltage to zero when the buck is disabled. this ensures that the output of the buck is always in a well - defined state, whether or not it is enabled. the adp2370 does not include th is output discharge function. short - circuit protection the adp2370 / adp2371 include frequ ency foldback to prevent output current runaway on a hard short. when the voltage at the feedback pin falls below 0.3 v, indicating the possibility of a hard short at the output, the switching frequency is reduced to 1/4 of the internal oscillator frequenc y. the reduction in the switching frequency gives more time for the inductor to dis - charge, preventing a runaway of output current. under v oltage lockout to protect against battery discharge, an under voltage lockout (uvlo) circuit is incorporated in to the adp2370 / adp2371 . when the input voltage drops below the uvlo threshold, the adp2370 / adp2371 shu ts down, and both the power switch and synchronous rectifier turn off. once the input voltage rises above the uvlo threshold, the soft start period is initiated and the device is enabled. thermal protection in the event that the junction temperature on either the adp2370 or adp2371 rise s above 150c, the thermal shutdown protec - tion circuit turns off the regulator. extreme junction temperature can be the result of high current operation, poor circuit board design, and/or high ambient te mperature. a 20 c hysteresis is included in the protection circuit so that when a thermal shut - down occurs, the device does not return to operation until the on - chip te mperature drops below 130c. when exiting a thermal shutdown, soft start is initiated. soft start the adp2370 / adp2371 have an internal soft start function that ramps the output voltage in a controlled manner upon startup, there by limiting the inrush current. this prevents possible input voltage drops when a battery or a high imped - ance power source is connected to the input of the converter . typical soft start time is 350 s . the adp2370 / adp2371 are also capable of starting up into a pre charged output capacitor. if soft start is invoked when the output capacitor charge is greater than zero, the device delays the start of switching until the internal soft start ramp reaches the corresponding fb voltage . this fea - ture prevents discharging the output capacitor at the beginning of soft start. current limit the adp2370 / adp2371 have protection circuitry t hat limit s the direction and amount of current to 1200 ma that flow s through the power switch and synchronous rectifier , cycle by cycle. the positive cu rrent limit on the power switch limits the amount of current that can flow from the input to the output. the negative current limit on the synchronous rectifier prevents the inductor current from reversing direction and flowing out of the load. a negative current limit is provided by t he adp2370 / adp2371 to prevent an excessive reverse inductor current when the switching section sinks current from the load in forced con tinuous con - duction mode. under negative current - limit conditions, both the high - side and low - side switches are disabled.
data sheet adp2370/adp2371 rev. a | page 23 of 32 100% duty cycle the adp2370 / adp2371 ente r a nd exit 100% duty cycle smoothly. the control loop seeks the next clock cycle while the high - side switch is engaged. when this occurs , the clock signal is masked and the pmos remains on. when the input voltage increases , the interna l v comp node decrease s i ts signal to the control loop ; thus, the device stop s skipping clock cycles and exit s 100% duty cycle. m2.00ms a ch1 4.90v t 32.20% 09531-074 ch1 1.00v b w ch3 50.0ma ? b w ch2 1.00v b w v in v out inductor current 1 2 3 figure 74 . transition into and out of dropout in psm m ode, v out = 5 v, 100 ma load m2.00ms a ch1 4.90v t 32.20% 09531-075 ch1 1.00v b w ch3 50.0ma ? b w ch2 1.00v b w v in v out inductor current 1 2 3 figure 75 . tran sition into and out of d ropout in pwm m ode, v out = 5 v, 100 ma load synchronizing it is possible to synchronize the adp2370 / adp2371 to an external clock within a frequency range from 400 khz to 1.6 mhz. the device automatically detects the rising edge of the first clock and synchronizes to the external clock. when the clock signal stop s, the device automatically switch es back to the internal clock and continue s o perati ng . the switchover is initiate d when no rising edge on the sync pin can be detected on the internal clock for a duration of four clock cycles. therefore, th e maximum delay time can be 6.7 s if the internal clock is running at its minimum frequency of 600 khz. during this time, there is no clock signal available. the output stops switching until the adp2370 circuitry switche s to the internal clock signal. if the device is synchronized to an external clo ck, the psm mode is disabled and the device stays in forced pwm mode. connect fsel to ground when synchronizing to a frequency range from 400 khz to 800 khz , and connect fsel to the input voltage when the external frequency is in the range of 800 khz to 16 00 khz. fsel has an internal pull - down resistor and default s to the 600 khz mode when fsel is unconnected. 1 2 3 internal 1.2mhz internal 600khz sync pwm clock (if fsel = 1) pwm clock follows sync until it misses 4 1.2mhz internal clock cycles pwm clock (if fsel = 0) 4 09531-076 figure 76 . typical sync timing m20.0s a ch4 2.00v t 20.0% 09531-077 ch1 5.00v b w ch3 200ma ? b w ch4 5.00v b w ch2 100mv b w sw v out inductor current sync 1 2 3 4 figure 77 . typical sync t ransient , 1.2 mhz to 800 k hz to 1.2 mhz m20.0s a ch4 2.00v t 20.0% 09531-078 ch1 5.00v b w ch3 200ma ? b w ch4 5.00v b w ch2 50.0mv b w sw v out inductor current sync 1 2 3 4 figure 78 . sync t ransient 1.2 mhz to 800 khz
adp2370/adp2371 data sheet rev. a | page 24 of 32 m2.00s a ch2 ?57.0mv t 20.0% 09531-079 ch1 5.00v b w ch3 200ma ? b w ch4 5.00v b w ch2 50.0mv b w sw v out inductor current sync 1 2 3 4 figure 79 . sync t ransient 800 k hz to 1.2 mhz power good the adp2370 / adp2371 power - good (pg) output indicates the state of the monitored output voltage. the pg function is an active high, open - drain output, requiring an external pull - up resistor that is typically supplied from the i/o supply r ail, as shown in figure 1 . when the s ensed output voltage is below 87% of its nominal value, the pg pin is held low. when the sensed output voltage rises above 92% of the nominal level, the pg line is pulled high after t reset . the pg pin rema ins high wh en the sensed output voltage is above 92% of the nominal output voltage level. the typical pg delay when the buck is in pwm mode is 2 0 s. figure 80 shows the typical pg operation during startup . figure 81 shows the pg operation when there is a large load transient that causes the output voltage to fall just below the pg threshold. when not using the pg function, remove the pull - up resistor and leave t he pg pin ei ther open or shorted to ground. m40.0s a ch3 3.40v t 10.00% 09531-080 ch1 500mv b w ch3 5.00v b w ch2 1.00v b w v out pg enable 3 2 1 figure 80 . typical pg timing at startup m1.00s a ch3 740ma t 10.00% 09531-081 ch1 500mv b w ch3 500ma? b w ch2 1.00v b w v out pg load current 1 2 3 figure 81 . typical pg timing with 200 ma to 1100 ma load t ransient
data sheet adp2370/adp2371 rev. a | page 25 of 32 applications informa tion adi sim p ower design tool adp2370 / adp2371 are supported by the adisimpower ? design tool set. adisimpower is a collection of tools that produce complete power designs optimized for a specific design goal . the tools enable the user to generate a full schematic, bill of materials, and calculate performance in minutes. adisimpower can optimize designs for cost, area, efficiency, and parts count taking into consideration the operating conditions and limita - ti ons of the ic and all real external components. for more information about , and to obtain adisimpower design tools, visit www.analog.com/adisimpower . users can also request an unpopulated board through the adisimpower tool. external component s election table 6 and table 7 list external component selection s for the adp2370 / adp2371 application circuit shown in figure 82. the selection of components is dependent on the input voltage, output voltage, and load current requirements. additionally, trade - offs among performance paramet ers , such as efficiency and transient response , are made by varying the choice of external components. selecting the induct or the high frequency switching of the adp2370 / adp2371 allows for the use of small surface - mount power inductors. the in ductor value affects the transi tion from pwm to psm, efficiency, output ripple, and current - limit values . use the following equation to cal - culate th e ideal inductance, which is derived from the inductor current slope compensation, for a given output voltage and switching frequency : sw out f v l = 478.0 2.1 the ripple current is calculated as follows: ? ? ? ? ? ? ? ? ? =? in out sw out l v v lf v i 1 where: f sw is the switching frequency in mhz (1.2 mhz typic al). l is the inductor value in h. the dc resistance (dcr) value of the selected inductor affects efficienc y ; however, a decrease in this value typically means an increase in root mean square (rms) losses in the core and skin. a mini mum requirement of the dc current rating of the inductor is for it to be equal to the maximum load current plus half of the inductor current ripple, as shown by the following equation: ) 2 ( )( l max load pk i ii ? + = output capacitor output ca pacitance is required to minimize the volta ge over shoot , voltage undershoot , and the ripple voltage present on the output. capacitors with low equivalent series resistance (esr) values produce the lowest output ripple; therefore, use capacitors such as the x5r dielectric . do not use y5v and z5u cap acitors. y5v and z5u capacitors are un suitable choices because of their large capacitance variation over temperature and their dc bias voltage changes. because esr is important, select the capacitor using the following equation: l ripple cout i v esr wher e: esr cout is the esr of the chosen capacitor . v ripple is the peak - to - peak output voltage ripple. use the following equations to determine the output capacitance: ripple sw in out vlf v c 2)2( ripple sw l out vf i c ? 8 increasing the output capacitor value has no effect on stability and may reduce output ripple and enhance load transient response. when choosing the output capacitor value, it is important to account for the loss of capacitance due to output voltage dc bias. input capacitor an input capacitor is req uired to reduce input voltage ripple, input ripple current, and source impedance. place the input capacitor as close as possible to the vin pin . a low esr x7r - or x5r - type capacitor is highly recommended to minimize the input voltage ripple. use the follow ing equation to determine the rms input current : in out in out max load cin v vvv ii ) ( )( ? in out in out max load v vvv i rms i ) ( )( ? adjustable output vo ltage programming the adp2370 / adp2371 feature an a djustable output voltage range from 0.8 v to 1 2 v. the output voltage is set by the ratio of two external resistors , r2 and r3 , as shown in figure 83 . the device servos the output to maintain the voltage at the fb pin at 0.8 v, refe renced to ground ; t he current in r 2 is then e qual to 0.8 v/r 3 plus the fb pin bias current. the bias current of the fb pin , 10 na at 25c, flows through r 2 into the fb pin. the output voltage i s calculated using the equation v out = 0.8 v (1 + r2 / r3 ) + ( fb i- bias )( r2 )
adp2370/adp2371 data sheet rev. a | page 26 of 32 t o minimize errors in the output voltage caused by the bias current of the fb pin, maintain a value of r 2 that is less than 2 50 k . for example, when r 2 and r 3 each equal 2 50 k, the output voltage is 1.6 v. the output voltage error introduced by the fb pin bias current is 2 .5 mv , or 0.15 6 %, assuming a typical fb pin bias current of 10 na at 25c. note that in shutdown mode , the o utput is turned off and the divider current is zero. select t he output inductor and capacitor as described in the selecting the inductor , output capacitor , and input capacitor se ctions , as well as table 6 for more information . efficiency efficiency is defined as the ratio of output power to input power. the high efficiency of the adp2370 / adp2371 has two distinct advantages. first, only a small amount of power is lost in the dc - to - dc con verter package, which in turn, reduces thermal constraints. second , high efficiency delivers the maximum output power for the given input power, thereby extending battery life in portable applications. power switch conduction losses power switch dc conduction losses are caused by the flow of output current through the p - channel power switch and the n- channel synchronous rectifier, which have internal resis - tances (r ds(on) ) associated with them. the amount o f power loss is approximated by 2 _)( _)( _ )) 1( ( out nonds ponds cond sw id rd r p ? + = w here : in out v v d = the internal resistance of the power switches increases with tem - perature and incr eases when the input voltage is less than 5.5 v. inductor losses inductor conduction losses are caused by the flow of current through the inductor, which has an internal resistance (dcr) associated with it. larger size inductors have smaller dcr, which can decrease inductor conduction losses. inductor core lo sses relate to the magnetic permeability of the core material . because the adp2370 / adp2371 are high switching fr equency dc - to - dc regulators, shielded ferrite core material is recommended because of its low core losses and low emi. to estimate the total amount of power lost in the inductor, use the following equation: p l = dcr i out 2 + core losses switching losses switching losses are associated with the current drawn by the driver to t urn - on and turn - off the power devices at the switching freque ncy. each time a power device gate is turned on and turned off, the driver transfers a charge from the input supply to the gate, and then from the gate to ground. estimate switching losses using the following equation: p sw = ( c gate_p + c gate_n ) v in 2 f sw where: c gate_p is the gate capacitance of the internal high - side switch. c gate_n is the gate capacitance of the intern al low - side switch. f sw is the switching frequency. the typical value for gate capacitances, c gate_p and c gate_n , is 150 pf . transition losses transition losses occur because the p - channel switch cannot turn on or turn off instantaneously. in the middl e of an sw node transition, the power switch provides all of the inductor current. the source - to - drain voltage of the power switch is half the input voltage, resulting in power loss. transition losses increase with both load current and input voltage and o ccur twice for each switching cycle. use the following equation to es t imate transition losses: p tran = v in /2 i out ( t r + t f ) f sw where: t r is the rise time of the sw node. t f is the fall time of the sw node. the typical value for the rise and fall t imes, t r and t f , is 2 ns . recommended buck ext ernal components the recommended external components for use with the adp2370 / adp2371 are listed in table 6 (inductors) and table 7 (capacitors). fsel en power good 6.8h v out = 3.3v v in = 6v c in 10f c out 10f agnd (exposed pad) vin sync on off adp2370/ adp2371 sw pg pgnd fb 1 2 3 4 8 7 6 5 09531-082 figure 82 . typical application, 1.2 mhz, fixed output
data sheet adp2370/adp2371 rev. a | page 27 of 32 fsel en power good r1 10k? r2 249k? r3 200k? 6.8h v out = 1.8v v in = 6v c in 10f c out 10f agnd (exposed pad) vin sync adp2370/ adp2371 sw pg pgnd fb 1 2 3 4 8 7 6 5 09531-083 on off figure 83 . typical application, 600 k hz, adjustable output table 6 . inductors vendor model frequency output voltage ideal value ( h) standard value (h) dimensions (mm) i sat (a) dcr (m) coilcraft xfl4020 - 222m e 1.2 mhz 1.2 2.5 2.2 4 4 2 4.1 24 coilcraft xfl4020 - 332m e 1.2 mhz 1.5 3.1 3.3 4 4 2 3.1 38 coilcraft xfl4020 - 332m e 1.2 mhz 1.8 3.8 3.3 4 4 2 3.1 38 coilcraft x fl4020 - 472m e 1.2 mhz 2.5 5.2 4.7 4 4 2 2.0 57 coilcraft xal4030 - 682me 1.2 mhz 3.0 6.3 6.8 4 4 3 1.9 74 coilcraft xal4030 - 682me 1.2 mhz 3.3 6.9 6.8 4 4 3 1.9 74 coilcraft xal4040 - 103me 1.2 mhz 5 10.5 10 4 4 4 1.5 92 coilcraft lps6235 - 183 ml 1.2 mhz 9 18.8 18 6 6 3.5 1.7 14 coilcraft xfl4020 - 472m e 600 khz 1.2 5.0 4.7 4 4 2 2.0 57 coilcraft xal4030 - 682me 600 khz 1.5 6.3 6.8 4 4 3 1.9 74 coilcraft xal4030 - 682me 600 khz 1.8 7.5 6.8 4 4 3 1.9 74 coilcraft xal4040 - 103me 600 k hz 2.5 10.5 10 4 4 4 1.5 92 coilcraft xal4040 - 103me 600 khz 3.0 12.6 10 4 4 4 1.5 92 coilcraft xal4040 - 153me 600 khz 3.3 13.8 15 4 4 4 1.3 120 coilcraft lps6235 - 223ml 600 khz 5 20.9 22 6 6 3.5 1.6 145 coilcraft lps6235 - 333ml 600 khz 9 3 7.7 33 6 6 3.5 1.3 130 table 7 . 10 f capacitors vendor model case size voltage rating location input v oltage output voltage murata grm32er7ya106ka12 1210 35 input or output <15 v murata grm32dr61e106ka12 1210 25 input or output <12 v murata grm31cr61c106ka88 1206 16 input or outp ut <8 v murata grm32er7ya106ka12 1210 35 input or output <12 v murata grm32dr61e106ka12 1210 25 input or output <9 v murata grm31cr61c106ka88 1206 16 input or output <7 v murata grm21br61c106ke15 0805 16 output <2.5 v
adp2370/adp2371 data sheet rev. a | page 28 of 32 capacitor selection outpu t capacitor the adp2370 / adp2371 are designed for operation with small, space - saving c eramic capacitors, but function with most commonly used ca pacitors provided that the effective series resistance (esr) value is carefully considered . the esr of the output capacitor affects stability of the control loop. a minimum output capa ci - tance of 7 f with an esr of 10 m? or less is recommended to ensure stability of the adp2370 / adp2371 . transient response to changes in load current is also affected by output capacitance. using a larger value of output capacitance improves the transient res ponse of the adp2370 / adp2371 to large changes in load current. figure 84 shows the transient response for an output capacita nce value of 10 f. m20.0s a ch1 560ma 1 2 3 t 10.40% 09531-084 ch1 500ma ? b w ch3 500ma ? b w ch2 50.0mv b w load current v out inductor current figure 84 . output transient response, v out2 = 1.8 v, c out = 10 f, 300 ma to 800 ma, load current rise time = 200 ns input bypass capacitor connecting a 1 0 f capacitor from vin to gnd reduces the cir cuit sen sitivity to the pcb layout, especially when long input traces or high source impedance are encountered . if greater than 10 f of output capacitance is required, increase the input capacitor to match it to improve the transient response . input and output ca pacitor properties use any good quality ceramic capacitors with the adp2370 / adp2371 ; however they must meet the minimum capacitance and maximum esr requirem ents. cer amic capacitors are manu - factured with a variety of dielectrics, each with different behavior over temperature and applied voltage. capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bia s conditions. x5r or x7r dielectric capacitor s with a voltage rating of 6.3 v to 25 v are recommended for best performance. y5v and z5u dielectrics are not recommended because of their poor temperature and dc bias characteristics. figure 85 depicts the capacitance vs. vol tage bias characteristic of a several 10 f capacitors in different case sizes and voltage ratings . the voltage stability of a capacitor is strongly influenced by the capacitor size and voltage rating . in general , a capacitor in a larger package or higher voltage rating exhibits better stability. the temperature variation of the x5r dielectric is about 15% over the ?40c to +85c tempera ture range and is not a function of package or voltage rating. 0 1 2 3 4 5 6 7 8 9 10 11 12 0 5 10 15 20 25 30 35 ca p aci t ance (f) dc bias vo lt age (v) 10 f/25 v /1210 10 f/35 v /1210 10 f/16 v /0805 10 f/16 v /1206 09531-085 figure 85 . capacitance vs. voltage characteristi c different case s izes use equation 1 to determine the worst - case capacitance , accounting for capacitor variation over temperature, component tolerance, and voltage. c eff = c bias (1 ? tempco ) (1 ? tol ) (1) where: c bias is the effective capacitance at the operating voltage. tempco is the worst - case capacitor temperature coefficient. tol is the worst - case component tolerance. in this example, the worst - case tempco over ?40 c to +85 c is assumed to be 15% for an x5r dielectric. the tolerance of the capacitor (tol) is assumed to be 10%, and c bias is 8.53 f at 12 v for the 10 f, 3 5 v capacitor in a 1210 package (see figure 85 ). substituting these values in equation 1 yields c eff = 8.53 f (1 ? 0.15) (1 ? 0.1) = 6.53 f ther efo re, the capacitor chosen in this example meets the minimum capacitance requirement of the adp2370 / adp2371 over temperature and tolerance at the chosen output voltage. to guarantee the performance of the adp2370 / adp2371 , it is imperative that the effects of dc bias, temperature, and tolerances of the capacitors are evaluated for each application.
data sheet adp2370/adp2371 rev. a | page 29 of 32 thermal consideratio ns in most applications, the adp2370 / adp2371 do not di ssipate much heat due to their hig h efficiency. however, in applications with high ambient temperature and high supply voltage - to - output voltage differential, the heat dissipated in the package may be large enough to cause the junction temperature of the d ie to exceed the 125 c maximum. if the junction temperature of the adp2370 / adp2371 exceeds 150c, the regulator enters thermal shutdown. the regulator recovers only after the junction temper ature has fallen below 130c, this helps to prevent any permanent damage to the ic. thermal analysis for the chosen application is clearly very important to guarantee reliable operation under all conditions. the junction temperatur e of the die is the sum of the ambient temperature of the environment and the temperature rise of the package due to the power dissipation, as shown in equation 2. to guarantee reliable operation, the junction temperature of the adp2370 / adp2371 must not exceed 125c. to ensure the junc - tion temper ature stays belo w this maximum value, the user must be aware of the parameters that contribute to junction temperature chang es. these parameters include ambient temperature , power dissipa tion in the power device, and the thermal resistance between the junction an d ambient air ( ja ). the ja number is dependent on the package assembly compounds that are used and the amount of pcb copper soldered to the package gnd and e pa d . table 8 shows typical ja values of the 8 - lead, 3 mm 3 mm lfcsp for various pcb copper sizes. table 8 . typical ja values copper size (mm 2 ) ja (c/w) 25 1 162.2 100 124.1 5 00 68.7 1000 56.5 6400 42.4 1 the device is soldered to minimum size pin traces. the junction temperat ure of the adp2370 / adp2371 is calculated from the following equation: t j = t a + ( p d ja ) (2) where: t a is the ambient temperature. p d is the total power dissipation in the die, given by p d = p buck = p sw + p tran + p sw_cond (3 ) where: p sw , p tran , and p sw_cond are defined in the efficiency section. for a given ambient temperature and total power dissipation, there exists a minimum copper size requirement for the pcb to ensure the junction temperature does not rise above 125c. the following figures ( figure 86 to figure 89) show junction temperature calculations for different ambient temperatur es, total power dissipation, and areas of pcb copper. 25 35 45 55 65 75 85 95 105 1 15 125 135 145 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 junction temper a ture (c) total power dissi pa tion (w) 6400mm 2 500mm 2 100mm 2 t j max 09531-086 figure 86 . junction temperature vs. power dissipation, t a = 25c 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 junction temper a ture (c) total power dissi pa tion (w) 09531-087 50 60 70 80 90 100 1 10 120 130 140 6400mm 2 500mm 2 100mm 2 t j max figure 87 . junction temperature vs. power dissipation, t a = 50c 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 junction temper a ture (c) total power dissi pa tion (w) 09531-088 6400mm 2 500mm 2 100mm 2 t j max 65 75 85 95 105 1 15 125 135 145 figure 88 . junction temperature vs. power dissipation, t a = 65c
adp2370/adp2371 data sheet rev. a | page 30 of 32 0 0.2 0.6 0.4 0.8 1.0 junction temper a ture (c) total power dissi pa tion (w) 09531-089 6400mm 2 500mm 2 100mm 2 t j max 85 95 105 1 15 125 135 figure 89 . junction temperature vs. power dissipation, t a = 85c in cases where the board temperature is known, use the thermal charact erization parameter, jb , to estimate the junction temper - ature rise. maximum junction temperature (t j ) is calculated from the board temperature (t b ) and power dissipation (p d ) using the formula : t j = t b + ( p d jb ) (5) the typical jb value for the 8- lead, 3 mm 3 mm lfcs p is 22.2 c / w. 09531-090 20 40 60 80 100 120 140 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 junction temper a ture (c) total power dissi pa tion (w) 25 c 50 c 65 c 85 c t j max figure 90 . junction temperature vs. power dissipation, different board temperatures pcb layout considera tions improve heat dissipation from the package by increasing the amount of copper attached to the pins of t he adp2370 / adp2371 . however, as listed in table 8 , a point of diminishing returns is eventually reached, beyond which an in crease in the copper size does not yield significant heat dissipation benefits. poor layout can affect the adp2370 / adp2371 buck performance causing electr omagnetic in terference (emi), poor electromagnetic compa tibility (emc) performance, ground bounce, and voltage losses; thus, regulation and stability can be affected. implement a good pcb layout to ensure optimum performance by applying the following rules: ? place the inductor, input capacitor, and output capacitor close to the ic using short tracks. these components carry high switching frequencies and long, large tracks act like antennas. ? route the output voltage path away from the inductor and sw node to minimize no ise and magnetic interference. ? use a ground plane with several vias connected to the component - side ground to reduce noise interference on sensitive circuit nodes. ? use of 0402 - size or 0603 - size capacitors achieves the smallest possible footprint solution on boards where area is limited.
data sheet adp2370/adp2371 rev. a | page 31 of 32 09531-091 figure 91 . pcb layout, top 09531-092 figure 92 . pcb layout, bottom
adp2370/adp2371 data sheet rev. a | page 32 of 32 packaging and ordering information outline dimensions 1 12008- a pin 1 indic at or (r 0.2) exposed p ad bot t om view top view 1 4 8 5 index are a 3.00 bsc sq sea ting plane 0.80 0.75 0.70 0.30 0.25 0.18 0.05 max 0.02 nom 0.80 max 0.55 nom 0.20 ref 0.50 bsc coplanarity 0.08 2.48 2.38 2.23 1.74 1.64 1.49 0.50 0.40 0.30 compliant to jedec standards mo-229-weed-4 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 93 . 8- lead lead f ra me chip scale package [lfcsp] (cp -8-5) dimensions shown in millimeters ordering guide model 1 buck output voltage (v) temperature range package description package option branding adp2370acpz - 1.2-r7 1.2 ? 40 c to + 125 c 8- lead lfcsp cp -8-5 ll4 adp2370acpz - 1.5-r7 1.5 ?40c to +125c 8- lead lfcsp cp -8-5 ll5 adp2370acpz - 1.8-r7 1.8 ?40c to +125c 8- lead lfcsp cp -8-5 ll6 adp2370acpz - 2.5-r7 2.5 ?40c to +125c 8- lead lfcsp cp -8-5 ll7 adp2370acpz - 3.0-r7 3.0 ?40c to +125c 8- lead lfcsp cp -8-5 ll8 adp2370acpz - 3.3-r7 3.3 ?40c to +125c 8- lead lfcsp cp -8-5 ll9 adp2370acpz - 5.0-r7 5.0 ?40c to +125c 8- lead lfcsp cp -8-5 llb adp2370acpz -r7 adjustable ?40c to +125c 8- lead lfcsp cp -8-5 lgz adp2371acpz - 1.2 - r7 1 .2 with qod ?40c to +125c 8 - lead lfcsp cp - 8 - 5 llj adp2371acpz - 1.8-r7 1.8 with qod ?40c to +125c 8- lead lfcsp cp -8-5 llk adp2371acpz - 3.3-r7 3.3 with qod ?40c to +125c 8- lead lfcsp cp -8-5 lll adp2371acpz -r7 adjustable with qod ?40c to +125c 8- lead lfcsp cp -8-5 llm adp2370cpz - redykit redykit 1 z = rohs compliant part. ? 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09531 -0- 5 /12(a )

▲Up To Search▲

Price & Availability of XAL4030-682ME

	To Download XAL4030-682ME Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .